发明公开
EP1962421A1 Calibration circuit for calibrating an adjustable capacitance of an integrated circuit having a time constant depending on said capacitance
审中-公开
基本信息:
- 专利标题： Calibration circuit for calibrating an adjustable capacitance of an integrated circuit having a time constant depending on said capacitance
- 专利标题（中）：用于校准集成电路的可调电容的时间常数依赖于电容校准电路
- 申请号：EP07425100.0 申请日：2007-02-23
- 公开(公告)号：EP1962421A1 公开(公告)日：2008-08-27
- 发明人： Confalonieri, Pierangelo , Martignone, Riccardo , Zamprogno, Marco
- 申请人： STMicroelectronics S.r.l.
- 申请人地址： Via C. Olivetti, 2 20041 Agrate Brianza (Milano) IT
- 专利权人： STMicroelectronics S.r.l.
- 当前专利权人： STMicroelectronics S.r.l.
- 当前专利权人地址： Via C. Olivetti, 2 20041 Agrate Brianza (Milano) IT
- 代理机构： Carangelo, Pierluigi
- 主分类号： H03H1/02
- IPC分类号： H03H1/02 ; H03H7/01
摘要：
A calibration circuit (30) for calibrating an adjustable capacitance (C var (REG_BUS)) of a circuit (31) having a time constant depending on said adjustable capacitance, the calibration circuit (30) being such as to output a calibration signal (REG_BUS) carrying information for calibrating said capacitor (C var (REG_BUS)) and including a calibration loop (RC_DEL, DFF, TG_SAR) comprising:
- a controllable capacitance unit (RC_DEL) suitable to receive a control signal (SAR_BUS) and including at least one array of switched capacitors (C_AR1, CAR_2), that can be activated by means of the control signal (SAR_BUS), the unit (RC_DEL) being such as to output a first signal (OUT_DEL) characterized by a parameter depending on the amount of capacitance of the array (C_AR1, CAR_2) activated by the control signal (SAR_BUS);
- a comparison unit (DFF) suitable to receive said first signal (OUT_DEL) to assess whether said parameter meets a preset condition and to output a comparison signal (OUT_DFF) representative of the assessment result;
- a control and timing logic unit (TG_SAR) suitable to receive the comparison signal (OUT_DFF) to change this control signal (SAR_BUS) based on said comparison signal (OUT_DFF),
characterized in that
said first signal (OUT_DEL) is a logic signal and said parameter is a time parameter of said first signal.
摘要（中）：
- a controllable capacitance unit (RC_DEL) suitable to receive a control signal (SAR_BUS) and including at least one array of switched capacitors (C_AR1, CAR_2), that can be activated by means of the control signal (SAR_BUS), the unit (RC_DEL) being such as to output a first signal (OUT_DEL) characterized by a parameter depending on the amount of capacitance of the array (C_AR1, CAR_2) activated by the control signal (SAR_BUS);
- a comparison unit (DFF) suitable to receive said first signal (OUT_DEL) to assess whether said parameter meets a preset condition and to output a comparison signal (OUT_DFF) representative of the assessment result;
- a control and timing logic unit (TG_SAR) suitable to receive the comparison signal (OUT_DFF) to change this control signal (SAR_BUS) based on said comparison signal (OUT_DFF),
characterized in that
said first signal (OUT_DEL) is a logic signal and said parameter is a time parameter of said first signal.
用于校准（在具有时间常数取决于所述可调电容的电路（31）的可调节的电容（C VAR（REG_BUS））的校准电路（30），所述校准电路（30）被检查，以输出一个校准信号REG_BUS ）携带信息用于校准所述电容器（C VAR（REG_BUS）），并且包括一个校准循环（RC_DEL，DFF，TG_SAR），包括： - 一个可控电容单元（RC_DEL）适合于接收控制信号（SAR_BUS）和包括至少一个 开关电容器（C_AR1，CAR_2）的阵列也可以由控制信号（SAR_BUS），单元（RC_DEL）的方式来激活正被检查，以输出由参数为特征的第一信号（OUT_DEL）上的电容的量根据 由控制信号（SAR_BUS）激活阵列（C_AR1，CAR_2）的; - 一个比较单元（DFF），其适于接收所述第一信号（OUT_DEL）评估是否所述参数是否满足预设条件，并输出比较信号（OUT_DFF）代表评估结果的一个; - 控制和定时逻辑单元（TG_SAR）适合于基于所述比较信号（OUT_DFF）接收比较信号（OUT_DFF）来改变该控制信号（SAR_BUS）表示，在这特点第一信号（OUT_DEL）是一个逻辑信号，并且 所述参数是所述第一信号的时间参数。
IPC结构图谱:
| H | 电学 |
| --H03 | 基本电子电路 |
| ----H03H | 阻抗网络，例如谐振电路；谐振器 |
| ------H03H1/00 | 未指明电工作模式或能应用于多于一种网络类型的阻抗网络的结构零部件 |
| --------H03H1/02 | .RC网络的，例如滤波器 |