发明公开
EP1932173A2 METHOD FOR FABRICATING LOW RESISTANCE, LOW INDUCTANCE INTERCONNECTIONS IN HIGH CURRENT SEMICONDUCTOR DEVICES
审中-公开
基本信息:
- 专利标题： METHOD FOR FABRICATING LOW RESISTANCE, LOW INDUCTANCE INTERCONNECTIONS IN HIGH CURRENT SEMICONDUCTOR DEVICES
- 专利标题（中）：PROCESS FOR化合物与高功率半导体元件低电阻和低电感的制备
- 申请号：EP06814056.5 申请日：2006-08-31
- 公开(公告)号：EP1932173A2 公开(公告)日：2008-06-18
- 发明人： LANGE, Bernhard, P. , COYLE, Anthony, L. , MAI, Quang, X.
- 申请人： Texas Instruments Incorporated
- 申请人地址： P.O. Box 655474 Mail Station 3999 Dallas, Texas 75265-5474 US
- 专利权人： Texas Instruments Incorporated
- 当前专利权人： Texas Instruments Incorporated
- 当前专利权人地址： P.O. Box 655474 Mail Station 3999 Dallas, Texas 75265-5474 US
- 代理机构： Holt, Michael
- 优先权： US218408 20050901
- 国际公布： WO2007027994 20070308
- 主分类号： H01L21/44
- IPC分类号： H01L21/44
摘要：
A method for fabricating a low resistance, low inductance device for high current semiconductor flip-chip products. A structure is produced, which comprises a semiconductor chip (101) with metallization traces (102), copper lines in contact with the traces, and copper bumps located in an orderly and repetitive arrangement on each line so that the bumps of one line are positioned about midway between the corresponding bumps of the neighboring lines. A substrate is provided which has elongated copper leads with first and second surfaces, the leads oriented at right angles to the lines. The first surface of each lead is connected to the corresponding bumps of alternating lines using solder elements.- Finally, the assembly is encapsulated in molding compound so that the second lead surfaces remain un-encapsulated.
IPC结构图谱:
| H | 电学 |
| --H01 | 基本电气元件 |
| ----H01L | 半导体器件；其他类目未包含的电固体器件 |
| ------H01L21/00 | 专门适用于制造或处理半导体或固体器件或其部件的方法或设备 |
| --------H01L21/02 | .半导体器件或其部件的制造或处理 |
| ----------H01L21/027 | ..未在H01L21/18或H01L21/34组中包含的为进一步的光刻工艺在半导体之上制作掩膜 |
| ------------H01L21/18 | ...器件有由周期表第Ⅳ族元素或含有/不含有杂质的AⅢBⅤ族化合物构成的半导体，如掺杂材料 |
| --------------H01L21/44 | ....用H01L21/36至H01L21/428各组不包含的方法或设备在半导体材料上制造电极的 |