In a VTR signal processing circuit, a first reproduced color under signal and a second reproduced color under signal obtained by delaying by one or two horizontal period in synchronism with a predetermined clock signal are supplied to the first and second frequency converter circuits (1 and 2) respectively, a frequency signal having frequency 2n times that of a carrier used in frequency conversion for converting a frequency of the reproduced color under signal into a frequency corresponding to a standard color signal is produced by an oscillator circuit (7), this oscillation frequency is divided (11) such that it becomes the above mentioned carrier frequency, four carriers having phases 0 degree, 90 degrees, 180 degrees, and 270 degrees respectively are produced, the four carriers are selectively output and supplied to the first and second frequency converter circuits (1 and 2) such that an output signal of the first frequency converter circuit (1) and an output signal of the second frequency converter circuit (2) become in phase or inverted phase, and a color cross-talk between tracks is removed by adding the both output signals or subtracting one of the output signals from the other (4), the clock generator circuit (12-20) for generating a clock signal in synchronism with a horizontal sync signal separated from a reproduced luminance signal is provided and the delaying operation of the delay circuit is controlled by this clock signal.