A pipelined Viterbi decoder (100) includes a plurality of circuit stages and a synchronous clocking arrangement for controlling the operations of the circuits within each stage. Specifically, an input stage (110) converts multi-level input signals into streams of even and odd digital data samples. A parellel-precomputation stage (200) adaptively establishes a threshold range for each sample, while a sequence detection stage (300) designates one of the multiple levels for that sample and then determines the validity of that designation. Validity is determined in accordance with the sequence property of alternate samples in multi-level coding. Violations of the sequence property are corrected by a sequence correction stage (400) so that valid, coded data and clock signals are provided at the outputs of the decoder.