
基本信息:
- 专利标题: 守时系统主钟信号保持器
- 专利标题(英):Punctual system master clock signal keeps ware
- 申请号:CN201521098234.0 申请日:2015-12-25
- 公开(公告)号:CN205594325U 公开(公告)日:2016-09-21
- 发明人: 李玮 , 王翔 , 闫敏 , 袁海波 , 宋会杰 , 赵书江 , 张继海 , 广伟
- 申请人: 中国科学院国家授时中心
- 申请人地址: 陕西省西安市临潼区书院东路3号
- 专利权人: 中国科学院国家授时中心
- 当前专利权人: 中国科学院国家授时中心
- 当前专利权人地址: 陕西省西安市临潼区书院东路3号
- 代理机构: 西北工业大学专利中心
- 代理人: 顾潮琪
- 主分类号: G04G7/00
- IPC分类号: G04G7/00 ; G04G5/00
The utility model provides a punctual system master clock signal keeps ware, data acquisition unit with activestandby clock correction, master clock and third party's clock clock correction, be equipped with the clock and compare data transmission to data processing unit with third party's clock clock correction and punctual clock ensemble, data processing element calculate obtains the master clock volume of controlling and is equipped with the clock volume of controlling, detects the atomic clock abnormal conditions simultaneously, control is sent the master clock volume of controlling and is equipped with the clock volume of controlling to the phase place fine setting appearance of activestandby clock with display element, sends the hold instruction to the phase -locked loop circuit during master clock trouble to switch to being equipped with the clock, power combiner has input behind master clock and the output signal parallel connection that is equipped with the clock sample voltage storage control function's phase -locked loop to regard the output of phase -locked loop as output signal. The utility model discloses can real -time detection master clock trouble, realize the continuity and the uniformity of high accuracy master clock time frequency signal's output.