![基于CRIO平台的双路IEC61850报文收发装置](/CN/2013/2/85/images/201320425260.jpg)
基本信息:
- 专利标题: 基于CRIO平台的双路IEC61850报文收发装置
- 专利标题(英):Dual-path IEC61850 message receiving and transmitting device based on CRIO (Core-Router Integrated Overlay) platform
- 申请号:CN201320425260.4 申请日:2013-07-17
- 公开(公告)号:CN203278857U 公开(公告)日:2013-11-06
- 发明人: 李鹏 , 刘和志 , 刘钊 , 全智 , 孟艳 , 卜京 , 殷明慧 , 徐嘉
- 申请人: 国家电网公司 , 国网重庆市电力公司江津供电分公司 , 南京理工大学
- 申请人地址: 北京市西城区长安街86号
- 专利权人: 国家电网公司,国网重庆市电力公司江津供电分公司,南京理工大学
- 当前专利权人: 国家电网公司,国网重庆市电力公司江津供电分公司,南京理工大学
- 当前专利权人地址: 北京市西城区长安街86号
- 代理机构: 重庆市恒信知识产权代理有限公司
- 代理人: 刘小红
- 主分类号: H04L12/02
- IPC分类号: H04L12/02 ; H04B10/27 ; H04L12/947
The utility model discloses a dual-path IEC61850 message receiving and transmitting device based on a CRIO (Core-Router Integrated Overlay) platform. The device comprises a Flash memory module, a power conversion module, an FPGA (Field Programmable Gate Array) module, an optical network port I, an optical network port II, a PHY (Physical Layer) chip and an crystal oscillator, wherein the optical network port I and the optical network port II are respectively connected with the PHY chip; the PHY chip is connected with the FPGA module through an FPGA bus; the FPGA module is connected with the Flash memory module through the FPGA bus; a power input terminal of the FPGA module is connected with the power conversion module; an output terminal of the crystal oscillator is connected with a clock input port of the FPGA module; and the FPGA module is externally connected with the CRIO platform through an SPI (Serial Peripheral Interface) bus and used for receiving a synchronous clock signal transmitted by the CRIO platform through the SPI bus. As the device is used, the functions of acquisition, analysis, transmission and the like of IEC61850 messages can be finished conveniently; and the dual paths of the optical network ports can be independently used for receiving and transmitting the message.