The embodiment of the utility model discloses a device for executing a signal processing operation. The device comprises a memory cell, an address generating unit functionally connected to the memory cell and used for receiving and writing-in of data, a register file system functionally connected to the address generating unit and used for receiving data, writing-in of values and storing the value in an array of a register memory, a multiply-accumulating execution unit functionally connected to the register file system and used for receiving, writing-in, matching, multiplying, and adding the data values and writing-in of sum and a multiplexer unit functionally connected to the register system, connected to the address generating unit and used for receiving the data. In a grading scheme, the register file system is organized. Firstly, the positions of individual register memories are matched to form paired register units, and then the paired register units are organized to be different sets of register units. The address generating unit places the value from the memory cell into the register.