![具有全环栅器件的自对准栅极端盖(SAGE)架构](/CN/2019/1/87/images/201910438948.jpg)
基本信息:
- 专利标题: 具有全环栅器件的自对准栅极端盖(SAGE)架构
- 专利标题(英):SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITH GATE-ALL-AROUND DEVICES
- 申请号:CN201910438948.8 申请日:2019-05-24
- 公开(公告)号:CN110634863A 公开(公告)日:2019-12-31
- 发明人: B.古哈 , W.徐 , L.P.古勒 , D.M.克鲁姆 , T.加尼
- 申请人: 英特尔公司
- 申请人地址: 美国加利福尼亚州
- 专利权人: 英特尔公司
- 当前专利权人: 英特尔公司
- 当前专利权人地址: 美国加利福尼亚州
- 代理机构: 中国专利代理(香港)有限公司
- 代理人: 张凌苗; 闫小龙
- 优先权: 16/017966 2018.06.25 US
- 主分类号: H01L27/088
- IPC分类号: H01L27/088
Self-aligned gate endcap (SAGE) architectures with gate-all-around devices. Self-aligned gate endcap (SAGE) architectures with gate-all-around devices, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate and having a length in a first direction. A nanowire is over the semiconductor fin. A gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures (1020) is included, where a first of the pair of gate endcap isolation structures is spaced equally from a first side of the semiconductor fin as a second of the pair of gate endcap isolation structures is spaced from a second side of the semiconductor fin.
IPC结构图谱:
H | 电学 |
--H01 | 基本电气元件 |
----H01L | 半导体器件;其他类目未包含的电固体器件 |
------H01L27/00 | 由在一个共用衬底内或其上形成的多个半导体或其他固态组件组成的器件 |
--------H01L27/02 | .包括有专门适用于整流、振荡、放大或切换的半导体组件并且至少有一个电位跃变势垒或者表面势垒的;包括至少有一个跃变势垒或者表面势垒的无源集成电路单元的 |
----------H01L27/04 | ..其衬底为半导体的 |
------------H01L27/06 | ...在非重复结构中包括有多个单个组件的 |
--------------H01L27/085 | ....只包含场效应的组件 |
----------------H01L27/088 | .....有绝缘栅场效应晶体管的组件 |