
基本信息:
- 专利标题: 一种基于FPGA+RISC-V的隐私放大算法的实现装置
- 专利标题(英):Implementation device of privacy amplification algorithm based on FPGA + RISC-V
- 申请号:CN201910776703.6 申请日:2019-08-22
- 公开(公告)号:CN110516809A 公开(公告)日:2019-11-29
- 发明人: 秦刚 , 姜凯 , 赵鑫鑫 , 王子彤 , 李朋
- 申请人: 山东浪潮人工智能研究院有限公司
- 申请人地址: 山东省济南市高新区浪潮路1036号浪潮科技园S05楼北六层
- 专利权人: 山东浪潮人工智能研究院有限公司
- 当前专利权人: 山东浪潮人工智能研究院有限公司
- 当前专利权人地址: 山东省济南市高新区浪潮路1036号浪潮科技园S05楼北六层
- 代理机构: 济南信达专利事务所有限公司
- 代理人: 孙晶伟
- 主分类号: G06N10/00
- IPC分类号: G06N10/00 ; G06F7/58
The invention discloses an implementation device of a privacy amplification algorithm based on FPGA + RISC-V, and relates to the field of data processing. The system comprises an RISC-V processor andan FPGA. RISC-V is used as a core processor; wherein the FPGA is mainly used for realizing a calculation task of a privacy amplification algorithm; the RISC-V realizes scheduling and management tasksof the algorithm; the PE control module of the FPGA starts the PE module according to an implementation instruction issued by the RISC-V processor; the number of the started PE modules is adjusted according to the resource consumption of the FPGA; all the opened PE modules form an integral PE module; the whole PE module performs multiplexing according to the issued implementation instruction to meet the requirements of a front-end data generation system; by utilizing the device, a privacy amplification algorithm can be realized, the flexibility is high, the algorithm speed can be adjusted according to equipment requirements, the device is applied to a quantum random number generator and QKD equipment in quantum communication, and high-speed data generation and transmission are facilitated.
公开/授权文献:
- CN110516809B 一种基于FPGA+RISC-V的隐私放大算法的实现装置 公开/授权日:2022-05-24
IPC结构图谱:
G | 物理 |
--G06 | 计算;推算;计数 |
----G06N | 基于特定计算模型的计算机系统 |
------G06N10/00 | 量子计算机,例如基于量子力学现象的计算机系统 |