![闪存的制造方法](/CN/2018/1/256/images/201811281931.jpg)
基本信息:
- 专利标题: 闪存的制造方法
- 专利标题(英):Manufacturing method for flash memories
- 申请号:CN201811281931.8 申请日:2018-10-31
- 公开(公告)号:CN109309094A 公开(公告)日:2019-02-05
- 发明人: 田志 , 邵华 , 陈昊瑜
- 申请人: 上海华力微电子有限公司
- 申请人地址: 上海市浦东新区自由贸易试验区高斯路568号
- 专利权人: 上海华力微电子有限公司
- 当前专利权人: 上海华力微电子有限公司
- 当前专利权人地址: 上海市浦东新区自由贸易试验区高斯路568号
- 代理机构: 上海浦一知识产权代理有限公司
- 代理人: 郭四华
- 主分类号: H01L27/115
- IPC分类号: H01L27/115 ; H01L27/11521
The invention discloses a manufacturing method for flash memories. The method for manufacturing the memory area of a flash memory includes the following steps: step one, forming active areas, and finishing the making of the first gate structures of flash memory cells, wherein the active areas are separated by field oxide formed on the surface of a silicon substrate, and are in bar-shaped structures and in parallel arrangement, and the polycrystalline silicon control gates of the first gate structures in the same row are connected together and form polycrystalline silicon rows; step two, forming an etch barrier layer on the surface of the active areas that are not covered by the polycrystalline silicon rows; step three, performing self-aligned source area field oxide etching, and removing field oxide self-alignment in source area forming areas, etching areas being defined by the polycrystalline silicon rows and silicon self-alignment, and the etch barrier layer preventing the silicon surfaces of the active areas from generating etching during self-aligned source area field oxide etching; and step four, removing the etch barrier layer. The method can prevent the surfaces of the active areas in source areas from generating etching loss and roundness during SAS field oxide etching, and therefore, the performance of devices can be enhanced.
公开/授权文献:
- CN109309094B 闪存的制造方法 公开/授权日:2020-11-24
IPC结构图谱:
H | 电学 |
--H01 | 基本电气元件 |
----H01L | 半导体器件;其他类目未包含的电固体器件 |
------H01L27/00 | 由在一个共用衬底内或其上形成的多个半导体或其他固态组件组成的器件 |
--------H01L27/02 | .包括有专门适用于整流、振荡、放大或切换的半导体组件并且至少有一个电位跃变势垒或者表面势垒的;包括至少有一个跃变势垒或者表面势垒的无源集成电路单元的 |
----------H01L27/04 | ..其衬底为半导体的 |
------------H01L27/06 | ...在非重复结构中包括有多个单个组件的 |
--------------H01L27/105 | ....包含场效应组件的 |
----------------H01L27/112 | .....只读存储器结构的 |
------------------H01L27/115 | ......电动编程只读存储器 |