The invention discloses a memory structure and a manufacturing method thereof. The memory comprises a semiconductor substrate, at least two shallow trench isolations, an active region, a first dielectric layer, a floating gate, a second dielectric layer and a control gate. The shallow trench isolations are adjacently arranged in the semiconductor substrate. The active region is disposed in the semiconductor substrate and located between the shallow trench isolations. The first dielectric layer is disposed on the surface of the active region. The floating gate is disposed on the semiconductor substrate and has a stepped sidewall, and comprises an upper portion and a lower portion, wherein the width of the upper portion is smaller than the width of the lower portion, the lower portion stretches across the active region and extends to the shallow trench isolations and partially covers the shallow trench isolations. The second dielectric layer covers the floating gate. The control gate isdisposed on the second dielectric layer.