基本信息:
- 专利标题： 用于通信中的纠错编码的方法和装置
- 专利标题（英）：METHOD AND APPARATUS FOR ERROR CORRECTION CODING IN COMMUNICATION
- 申请号：CN201880000877.7 申请日：2018-03-16
- 公开(公告)号：CN108934186A 公开(公告)日：2018-12-04
- 发明人： 李重佑 , 提摩西·培林·费雪-杰费斯 , 邱茂清 , 陈威任 , 徐诚羿 , 陈儒雅 , 张晏硕
- 申请人： 联发科技股份有限公司
- 申请人地址： 中国台湾新竹科学工业园区
- 专利权人： 联发科技股份有限公司
- 当前专利权人： 联发科技股份有限公司
- 当前专利权人地址： 中国台湾新竹科学工业园区
- 代理机构： 北京三友知识产权代理有限公司
- 代理人： 刘久亮
- 优先权： 62/475,953 2017.03.24 US
- 国际申请： PCT/CN2018/079224 2018.03.16
- 国际公布： WO2018/171510 EN 2018.09.27
- 进入国家日期： 2018-07-25
- 主分类号： H04L1/00
- IPC分类号： H04L1/00 ; H03M13/11
Aspects of the disclosure provide an apparatus and a method for error correction based on a matrix. The apparatus includes memory and processing circuitry. The memory is configured to store the matrixassociated with a set of parity bits. The matrix having rows and columns includes elements having values corresponding to either a first state or a second state. The matrix also includes a row havingtwo elements with values corresponding to the first state. One of the two elements is a parity element corresponding to a parity bit associated with the row. Further, other elements in a same columnas the parity element have values corresponding to the second state. The processing circuitry is configured to implement error correction based on the matrix. In another embodiment, the processing circuitry is configured to encode a data unit by generating the set of parity bits from the data unit based on the matrix and to form a codeword that includes the data unit and the set of parity bits. The processing circuitry is also configured to decode a received codeword having a received data unit based on the matrix and to obtain a decoded data unit.
公开/授权文献:
- CN108934186B 用于通信中的纠错编码的方法和装置 公开/授权日：2020-06-12
IPC结构图谱:
| H | 电学 |
| --H04 | 电通信技术 |
| ----H04L | 数字信息的传输，例如电报通信 |
| ------H04L1/00 | 检测或防止收到信息中的差错的装置 |