基本信息:
- 专利标题： 可编程逻辑IC的块存储器布局和体系架构及其操作方法
- 专利标题（英）：BLOCK MEMORY LAYOUT AND ARCHITECTURE FOR PROGRAMMABLE LOGIC IC, AND METHOD OF OPERATING SAME
- 申请号：CN201680050047.6 申请日：2016-08-18
- 公开(公告)号：CN107924428A 公开(公告)日：2018-04-17
- 发明人： G·R·塔特 , C·C·王
- 申请人： 弗莱克斯-罗技克斯技术公司
- 申请人地址： 美国加利福尼亚州
- 专利权人： 弗莱克斯-罗技克斯技术公司
- 当前专利权人： 弗莱克斯-罗技克斯技术公司
- 当前专利权人地址： 美国加利福尼亚州
- 代理机构： 中国国际贸易促进委员会专利商标事务所
- 代理人： 郑宗玉
- 优先权： 62/213,080 2015.09.01 US
- 国际申请： PCT/US2016/047465 2016.08.18
- 国际公布： WO2017/040049 EN 2017.03.09
- 进入国家日期： 2018-02-28
- 主分类号： G06F17/50
- IPC分类号： G06F17/50 ; H01L27/118 ; H03K19/177
An integrated circuit comprising programmable/configurable logic circuitry includes a plurality of logic tiles, arranged in an array, wherein each logic tile includes logic circuitry and I/O connectedin an interconnect network via multiplexers. A first logic tile includes (i) a first portion of a perimeter which forms at least a portion of the periphery of the programmable/configurable logic circuitry and (ii) a second portion of a perimeter which is interior to such circuitry's periphery, wherein memory I/O is disposed on the second portion of the perimeter of the first logic tile. A secondlogic tile includes a second portion of a perimeter which is interior to the programmable/configurable logic circuitry's periphery and opposes the first logic tile's perimeter. Memory array(s), located between the second portions of the perimeters of the first and second logic tiles, is/are coupled to memory I/O of at least the first logic tile.
公开/授权文献:
- CN107924428B 可编程逻辑IC的块存储器布局和体系架构及其操作方法 公开/授权日：2022-03-15