![集成超高压电阻的集成电路器件及其制作方法](/CN/2016/1/77/images/201610389667.jpg)
基本信息:
- 专利标题: 集成超高压电阻的集成电路器件及其制作方法
- 专利标题(英):Integrated circuit device for integrated EHV (extra-high voltage) resistor and manufacturing method of integrated circuit device
- 申请号:CN201610389667.4 申请日:2016-06-02
- 公开(公告)号:CN107464852A 公开(公告)日:2017-12-12
- 发明人: 石金成 , 马万里 , 高振杰 , 李杰英 , 崔永军
- 申请人: 北大方正集团有限公司 , 深圳方正微电子有限公司
- 申请人地址: 北京市海淀区成府路298号方正大厦
- 专利权人: 北大方正集团有限公司,深圳方正微电子有限公司
- 当前专利权人: 北大方正集团有限公司,深圳方正微电子有限公司
- 当前专利权人地址: 北京市海淀区成府路298号方正大厦
- 代理机构: 北京路浩知识产权代理有限公司
- 代理人: 李相雨
- 主分类号: H01L29/8605
- IPC分类号: H01L29/8605 ; H01L29/06 ; H01L21/31
The invention discloses an integrated circuit device for an integrated EHV (extra-high voltage) resistor and a manufacturing method of the integrated circuit device. The method comprises the steps: forming an N-type well region and a P-type well region in a substrate, and forming field oxidation layers in some regions on the surfaces of the N-type well region and the P-type well region; forming silicon nitride layers and silicon oxide layers coating the silicon nitride layers in regions, in which high-voltage resistors are prefabricated, of the field oxidation layers; forming a gate oxide layer in a region which is not covered by the field oxidation layers; forming non-doped polysilicon on the silicon oxide layers, the gate oxide layer in the N-type well region and the gate oxide layer in the P-type well region; carrying out the doping of the non-doped polysilicon on the silicon oxide layers to form high-resistance polysilicon, carrying out the non-doped polysilicon on the gate oxide layers to form low-resistance polysilicon. The above method can achieve the integration of a high-voltage resistor which can bear a 500V voltage or more in an integrated circuit, saves the packaging cost, and improves the module reliability.