![一种二元域位宽可变模乘运算器](/CN/2016/1/179/images/201610899987.jpg)
基本信息:
- 专利标题: 一种二元域位宽可变模乘运算器
- 专利标题(英):Binary field bit-width-variable modular multiplication operator
- 申请号:CN201610899987.4 申请日:2016-10-17
- 公开(公告)号:CN106484366A 公开(公告)日:2017-03-08
- 发明人: 赵霞 , 陈佳旭 , 黄琰玲 , 梅灵 , 李冰 , 刘勇 , 董乾 , 陈帅 , 王刚
- 申请人: 东南大学
- 申请人地址: 江苏省无锡市新区菱湖大道99号
- 专利权人: 东南大学
- 当前专利权人: 东南大学
- 当前专利权人地址: 江苏省无锡市新区菱湖大道99号
- 代理机构: 南京苏高专利商标事务所
- 代理人: 柏尚春
- 主分类号: G06F7/72
- IPC分类号: G06F7/72
The invention discloses a modular multiplication operator implemented by a series-parallel combination way, and belongs to the field of elliptic curve cryptography algorithms. The binary field bit-width-variable modular multiplication operator comprises a partial product multiplication unit, a word level multiplication unit, an output cache unit, a data shifting unit and a control unit. The modular multiplication operator is based on a polynomial basis under a binary field; input data are read in an MSB-first (Most Significant Bit first) way; the step number of loop computing is controlled according to computing digits by a state machine; a word multiplication operation and a partial multiplication operation are performed concurrently in the steps; and lastly, computing results in all the steps are integrated, and output in series. The operating rate is increased in the series-parallel combination way, and the computing complexity is lowered. Meanwhile, a bit multiplier capable of computing data of a plurality of bit widths is designed internally, so that reutilization of a hardware structure is realized. Compared with the prior art, the modular multiplication operator is more advantageous on the aspects of area, flexibility and the like, and a relatively high operation rate is ensured at the same time.
公开/授权文献:
- CN106484366B 一种二元域位宽可变模乘运算器 公开/授权日:2018-12-14