The invention belongs to the technical field of data transmission, and in particular relates to a three-tap decision feedback equalizer having low power dissipation and used for a receiving end of a high-speed serial interface. The three-tap decision feedback equalizer comprises two data paths, respectively an odd data path and an even data path same in structure; each data path comprises a gain stage, an offset cancelling unit, a dynamic combiner summator, a dynamic latch summator, a buffer, a dynamic feedback stage and a splitter; the gain stages and the offset cancelling units in the odd and even data paths form a front equalizing end; the dynamic latch summators, the dynamic feedback stages and the buffers in the odd and even data paths form a first tap loop; the dynamic combiner summators and the splitters in the odd and even data paths form a third and third tap loops; and summation units of whole three tap modules are in a clock control implementation manner. The three-tap decision feedback equalizer disclosed by the invention has the characteristics of being low in power consumption, high in working rate and strong in equalizing capability.