
基本信息:
- 专利标题: 半导体器件、半导体晶片及半导体器件的制造方法
- 申请号:CN201510262495.X 申请日:2012-09-14
- 公开(公告)号:CN104934407B 公开(公告)日:2018-06-19
- 发明人: 吉泽和隆 , 江间泰示 , 森木拓也
- 申请人: 富士通半导体股份有限公司
- 申请人地址: 日本神奈川县横滨市
- 专利权人: 富士通半导体股份有限公司
- 当前专利权人: 富士通株式会社
- 当前专利权人地址: 日本神奈川县
- 代理机构: 隆天知识产权代理有限公司
- 代理人: 石海霞; 郑特强
- 优先权: 2011-201321 2011.09.15 JP
- 主分类号: H01L23/52
- IPC分类号: H01L23/52 ; H01L27/04 ; H01L21/77
A semiconductor device includes wiring layers formed over a semiconductor wafer, a via-layer between the wiring layers, conductive films in the wiring layers, and a via-plug in the via-layer connecting the conductive films of the wiring layers above and below, a scribe region at an outer periphery of a chip region along an edge of the semiconductor substrate and including a pad region in the vicinity of the edge, the pad region overlapping the conductive films of the plurality of wiring layers in the plan view, the plurality of wiring layers including first second wiring layers, the conductive film of the first wiring layer includes a first conductive pattern formed over an entire surface of said pad region in a plan view, and the conductive film of the second wiring layer includes a second conductive pattern formed in a part of the pad region in a plan view.
公开/授权文献:
- CN104934407A 半导体器件、半导体晶片及半导体器件的制造方法 公开/授权日:2015-09-23
IPC结构图谱:
H | 电学 |
--H01 | 基本电气元件 |
----H01L | 半导体器件;其他类目未包含的电固体器件 |
------H01L23/00 | 半导体或其他固态器件的零部件 |
--------H01L23/52 | .用于在处于工作中的器件内部从一个组件向另一个组件通电的装置 |