The invention discloses a packaging structure for reducing internal resistance of an MOS chip and a packaging method. The packaging structure comprises a silicon substrate, a first source electrode, a first drain electrode and a first grid electrode of at least one MOS transistor are arranged on the front side of the silicon substrate, blind holes corresponding to the drain electrodes are formed in the back side of the silicon substrate, and a metal layer is laid in the blind holes and the back side of the silicon substrate. The packaging structure can reduce the value of equivalent resistance of the drain electrodes of the MOS chip; besides, the blind holes are formed in the back side of the MOS chip, the strength of the MOS chip is enhanced, and the metal layer is formed in the blind holes and on the back side of the MOS chip so that the heat dissipation effect of the MOS chip can be greatly improved and breakover power consumption can be reduced. The process of conducting overall packaging first and then conducting cutting on the wafer level is adopted for the packaging method and has the advantages that overall cost is greatly lowered compared with current traditional packaging processes.