
基本信息:
- 专利标题: 一种多模可编程分频器
- 专利标题(英):Multi-mode programmable frequency divider
- 申请号:CN201310138544.X 申请日:2013-04-19
- 公开(公告)号:CN104113325A 公开(公告)日:2014-10-22
- 发明人: 易律凡 , 彭关超 , 刘永才 , 谢豪律 , 周栋梁
- 申请人: 中兴通讯股份有限公司
- 申请人地址: 广东省深圳市南山区高新技术产业园科技南路中兴通讯大厦法务部
- 专利权人: 中兴通讯股份有限公司
- 当前专利权人: 深圳市中兴微电子技术有限公司
- 当前专利权人地址: 518055 广东省深圳市南山区西丽街道留仙大道中兴工业园
- 代理机构: 北京派特恩知识产权代理有限公司
- 代理人: 蒋雅洁
- 主分类号: H03K23/66
- IPC分类号: H03K23/66
The invention discloses a multi-mode programmable frequency divider. The multi-mode programmable frequency divider includes the following components of: cascaded 2/3 frequency division units, wherein the number of units without no frequency dividing ratio extension bits and the number of units with extension bits are Ne and n-Ne respectively; a real-time power consumption control circuit which is composed of n-Ne-1 stages of two-input AND gates; and a power source switching control transistor. Inverting signals of a frequency dividing ratio control bit of the n-th stage of frequency division unit is connected with a power source control bit of the n-th stage of frequency division unit, and the inverting signals and inverting signals of a frequency dividing ratio control bit of the n-1-th stage of frequency division unit are connected with the input ends of the n-th stage of AND gate, and the output end of the n-th stage of AND gate is connected with a power source control bit of the n-1-th stage of frequency division unit, and the output end of the n-th of stage AND gate and inverting signals of a frequency dividing ratio control bit of the n-2-th stage of frequency division unit are correspondingly connected with the input ends of an n-1-th stage of AND gate; connection is performed sequentially as the above steps until connection of the n-Ne-th stage of frequency division unit and the n-Ne-1-th stage of AND gate is completed; the drain of the power source switching control transistor is connected with power source ends of the frequency division units with extension bits; the source of the power source switching control transistor is connected with a power supplying power source; and the gate of the power source switching control transistor is connected with the power source control bits of the frequency division units with extension bits. With the multi-mode programmable frequency divider of the invention adopted, power consumption waste of the frequency divider can be avoided.
公开/授权文献:
- CN104113325B 一种多模可编程分频器 公开/授权日:2018-09-28
IPC结构图谱:
H | 电学 |
--H03 | 基本电子电路 |
----H03K | 脉冲技术 |
------H03K23/00 | 由计数链组成的脉冲计数器;由计数链组成的分频器 |
--------H03K23/40 | .选通信号或时钟信号加到所有各级的,即同步计数器 |
----------H03K23/66 | ..带有可变计数基数的,例如通过预置脉冲或增添脉冲或抑制脉冲改变计数基数的 |