The invention discloses an isolation type high voltage resistance field effect transistor (FET). A drift area of a drain region on a silicon substrate is extended to cover a whole source region, the isolation of a substrate of the source region and the silicon substrate is realized, and therefore the effects that the substrate electric potential of the FET cannot be affected by the electric potential of the silicon substrate, and the electric potential can be added independently can be achieved. The invention further provides a layout structure of the isolation type high voltage resistance FET. The layout structure of the isolation type high voltage resistance FET comprises the drain region, the source region, the drain region drift area, a drift region, a source region poly silicon field plate, grid electrodes and a drain region poly silicon field plate, wherein the source region poly silicon field plate, the grid electrodes and the drain region poly silicon field plate are all in U-shaped enclosed structures, and the drain region poly silicon field plate is located inside the source region poly silicon field plate and the grid electrodes. Due to the structure that the source region completely surrounds the drain region, and meanwhile, the substrate, drift region implantation and a doped region are adopted at a circular arc position at the bottom of a U-shaped inner layer to form an isolation voltage resistance ring, the situation that high voltage electric potential is located outside the position, and low voltage electric potential is located inside the position is avoided, breakdown voltage can be affected in a concentrative mode by a power line, and therefore the high voltage resistant capacity is achieved, and the area of a device is reduced at the same time.