The invention discloses a grapheme Hoare integrated circuit and a preparation method thereof. The grapheme Hoare integrated circuit comprises a silica-based complementary metal-oxide-semiconductor transistor (CMOS) circuit chip and a grapheme Hoare element. A plurality of interconnection electrodes and bonding electrodes are arranged on the periphery of a core circuit area of the chip. A passivation layer covers the surface area of the chip without the interconnection electrodes and the bonding electrodes. The interconnection electrodes and the bonding electrodes are respectively electrically connected with the bonding electrodes through metal wires under the passivation layer. An organic molecule layer and the grapheme Hoare element are successively arranged on the passivation layer which is above the core circuit area of the chip. Electrodes of the grapheme Hoare element are respectively connected with the interconnection electrodes through metal interconnection wires. Due to the fact that the surface of the Hoare integrated circuit is sealed by being covered with the passivation layer, only the bonding electrodes are showed, the bonding electrodes can conveniently be connected with external circuits in actual use. The grapheme Hoare integrated circuit is prepared completely through micromachining method, required chip area is small, preparation efficiency is high, and cost is low.