![导线架在芯片及芯片在导线架的多芯片堆叠结构](/CN/2007/1/29/images/200710145486.jpg)
基本信息:
- 专利标题: 导线架在芯片及芯片在导线架的多芯片堆叠结构
- 专利标题(英):Multi-chip stacking construction for lead frame on chip and chip on lead frame
- 申请号:CN200710145486.8 申请日:2007-09-14
- 公开(公告)号:CN101388380A 公开(公告)日:2009-03-18
- 发明人: 周世文 , 潘玉堂 , 林俊宏
- 申请人: 南茂科技股份有限公司 , 百慕达南茂科技股份有限公司
- 申请人地址: 中国台湾新竹县新竹科学工业园区研发一路1号
- 专利权人: 南茂科技股份有限公司,百慕达南茂科技股份有限公司
- 当前专利权人: 南茂科技股份有限公司,百慕达南茂科技股份有限公司
- 当前专利权人地址: 中国台湾新竹县新竹科学工业园区研发一路1号
- 代理机构: 中科专利商标代理有限责任公司
- 代理人: 周国城
- 主分类号: H01L25/00
- IPC分类号: H01L25/00 ; H01L25/065 ; H01L23/488 ; H01L23/495 ; H01L21/50 ; H01L21/60 ; H01L21/56
A package structure stacked with a plurality of chips comprises a lead frame, a first chip and a second chip, wherein the lead frame is formed by a plurality of inner pins and a plurality of outer pins, and the inner pin comprises a plurality of parallel first inner pin groups and a plurality of parallel second inner pin groups, and the first inner pin groups are oppositely arrayed with the tail ends of the second inner pin groups in an interval. A plurality of metal bonding pads are arranged on the active surface of the first chip close to the center region, and are fixed on the lower surfaces of the first inner pin groups and the second inner pin groups through a first adhesive coating, and some metal bonding pads are exposed, a second adhesive coating is formed on the back of the second chip, and the second chip is fixed on the upper surfaces of the first inner pin groups and the second inner pin groups through the second adhesive coating, and a metal wire for connecting the first chip is disconnected with the back of the second chip through the space formed by the thickness of the second adhesive coating.
IPC结构图谱:
H | 电学 |
--H01 | 基本电气元件 |
----H01L | 半导体器件;其他类目未包含的电固体器件 |
------H01L25/00 | 由多个单个半导体或其他固态器件组成的组装件 |